1. Field of the Invention
This invention is directed to asynchronous register circuits, in general, and to circuits which are used to asynchronously monitor the status of other logical circuits, in particular.
2. Prior Art
There are many types of data processing circuitry available in the current market. These circuits do and perform many functions. As the circuits increase in speed, complexity and capability, the systems are frequently called upon to perform many functions asynchronously. This asynchronous operation is intended to increase the speed of performance of the computing system.
However, with the use of asynchronous operation, other types of controls are frequently required to supplant the clock system which is used in synchronous machines. In the synchronous machines known to date, one approach is to synchronously (or in series) sample or monitor the operation of multiple subsystems or peripheral units associated with the computer system. Thus, all of the types of input are sampled to determine whether or not an operation should be performed. Consequently, the systems operate extraordinarily slowly.
On the other hand, attempts have been made to provide asynchronous operation. These asynchronous machines tend to operate on the basis that information is detected when it occurs and causes an interrupt in the computer operation as a function of the priority of the various inputs. However, this type of system is still subject to the difficulties of prioritizing the inputs which are being monitored. Moreover, the application of input signals from more than one of the monitored systems sometimes causes difficulties in prioritizing or proper handling thereof. For example, it is essential that a subsequent input signal from the control circuitry should not improperly impact the operation of the system while a prior input is being operated upon. Moreover, it is highly desirable to have the system operate in such a fashion that that the monitoring operation is effective only when the data processing system is ready to receive the input indicating signal.